Counterfeit Integrated Circuits: Detection and Avoidance by Mark M. Tehranipoor, Ujjwal Guin, Domenic Forte

By Mark M. Tehranipoor, Ujjwal Guin, Domenic Forte

This well timed and exhaustive learn bargains a much-needed exam of the scope and effects of the digital counterfeit alternate. The authors describe various shortcomings and vulnerabilities within the digital part provide chain, which can lead to counterfeit built-in circuits (ICs). not just does this booklet supply an evaluation of the present counterfeiting difficulties dealing with either the private and non-private sectors, it additionally bargains sensible, real-world recommendations for combatting this vast threat.

· is helping rookies and practitioners within the box by way of offering a complete historical past at the counterfeiting problem;

· provides cutting edge taxonomies for counterfeit forms, attempt equipment, and counterfeit defects, which permits for an in depth research of counterfeiting and its mitigation;

· presents step by step suggestions for detecting varieties of counterfeit ICs;

· bargains pragmatic and practice-oriented, sensible options to counterfeit IC detection and avoidance, for and government.

From the again Cover

This well timed and exhaustive learn bargains a much-needed exam of the scope and results of the digital counterfeit alternate. The authors describe a number of shortcomings and vulnerabilities within the digital part offer chain, which can lead to counterfeit built-in circuits (ICs). not just does this e-book offer an evaluate of the present counterfeiting difficulties dealing with either the private and non-private sectors, it additionally bargains useful, real-world strategies for combatting this large threat.

· is helping novices and practitioners within the box through delivering a complete heritage at the counterfeiting problem;

· provides leading edge taxonomies for counterfeit kinds, try out tools, and counterfeit defects, which permits for an in depth research of counterfeiting and its mitigation;

· offers step by step options for detecting types of counterfeit ICs;

· deals pragmatic and practice-oriented, life like ideas to counterfeit IC detection and avoidance, for and government.

About the Author

Mark (Mohammad) Tehranipoor is at present the Charles H. Knapp affiliate Professor of electric and machine Engineering division on the college of Connecticut.

His present study tasks contain: computer-aided layout and try out for CMOS VLSI designs, safeguard and belief, counterfeit IC detection and prevention, and trustworthy platforms layout at nanoscale. Prof. Tehranipoor has released over two hundred magazine articles and refereed convention papers and has given greater than one hundred twenty five invited talks and keynote addresses for the reason that 2006. moreover, he has released 5 books and ten e-book chapters. His tasks are subsidized via either the (SRC, Texas tools, Freescale, Comcast, Honeywell, LSI, Mentor photos, Cisco, Qualcomm, MediaTeck, etc.) and govt (NSF, ARO, MDA, DOD, DOE, etc.).

He is a recipient of numerous most sensible paper awards, the 2008 IEEE computing device Society (CS) Meritorious carrier Award, the 2012 IEEE CS striking Contribution, the 2010 IEEE CS such a lot winning Technical occasion for co-founding and chairing HOST Symposium, the 2009 NSF profession Award, the 2009 UConn ECE learn Excellence Award, and the 2012 UConn SOE awesome school consultant Award.

He serves at the application committee of greater than a dozen top meetings and workshops. Prof. Tehranipoor served because the visitor editor for JETTA, IEEE layout and try of pcs, and IEEE desktop Society Computing Now. He served as application Chair of the 2007 IEEE Defect-Based trying out (DBT) workshop, software Chair of the 2008 IEEE illness and information pushed checking out (D3T) workshop, Co-program Chair of the 2008 overseas Symposium on disorder and Fault Tolerance in VLSI platforms (DFTS), common Chair for D3T-2009 and DFTS-2009, and Vice-general Chair for NATW-2011.

He co-founded a brand new symposium known as IEEE foreign Symposium on Hardware-Oriented protection and belief (HOST) ()http://www.engr.uconn.edu/HOST/) and served as HOST-2008 and HOST-2009 normal Chair and proceed to function Chair of guidance Committee for HOST. he's additionally a co-founder of Trust-Hub (www.trust-hub.org). he's at the moment serving because the affiliate Editor-in-Chief (EIC) for IEEE layout and attempt of desktops, an affiliate Editor for JETTA, an affiliate Editor for magazine of Low strength Electronics (JOLPE), an affiliate Editor for ACM Transactions for layout Automation of digital platforms (TODAES), an IEEE exclusive Speaker, and an ACM individual Speaker.

Prof. Tehranipoor is a Senior Member of the IEEE, Golden center Member of IEEE laptop Society, and Member of ACM and ACM SIGDA.

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Additional resources for Counterfeit Integrated Circuits: Detection and Avoidance

Example text

Koushanfar, G. Qu, Hardware metering, in Proc. IEEE-ACM Design Automation Conference (2001), pp. 490–493 19. G. Contreras, T. Rahman, M. Tehranipoor, Secure split-test for preventing IC piracy by untrusted foundry and assembly, in Proc. International Symposium on Fault and Defect Tolerance in VLSI Systems (2013) 20. M. Tehranipoor, H. Salmani, X. Zhang, Integrated Circuit Authentication: Hardware Trojans and Counterfeit Detection (Springer, Zurich, 2014) 21. U. Guin, D. DiMase, M. Tehranipoor, A comprehensive framework for counterfeit defect coverage analysis and detection assessment.

Unfortunately, since ICs could be of various types (analog, digital or mixed signal) and sizes, a one-solution-fits-all approach for detection is hard to implement. Chapters 9–12 will focus on measures for the detection and avoidance of these components. References 1. J. com/press-release/designsupply-chain/reports-counterfeit-parts-quadruple-2009-challenging-us-defense-in 2. Information Handling Services Inc. com/ 3. com/information_sharing_high_risk_parts 4. org/ 5. org/home 6. S. S. military and other industries.

Burn-in, using accelerated temperature and voltage, is often performed to test latent defects in order to avoid the failures in the early operational stages of chips. All the rejected chips from various test process should be destroyed (if they are non-functional), downgraded (does not satisfy the specification), or otherwise be properly disposed of. However, if they are sold on the open market instead, either knowingly by an untrusted entity or by a third party who has stolen them, there will be an inevitable increase in their risk of failure.

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